Many storage systems use a logical-to-physical address table to convert a logical address received from a host in a read or write command to a physical address in non-volatile memory where data is to be read from or written to. The logical-to-physical address table is often stored in the non-volatile memory, but as searching the table in non-volatile memory can be time-consuming, some storage systems move the table from non-volatile memory to volatile memory (e.g., RAM), where the table can be searched faster. If the non-volatile memory space being mapped is small enough, the entire logical-to-physical address table can be cached in the volatile memory. However, when the memory space is very large, the logical-to-physical address table is very large and may not be able to be loaded in its entirety in volatile memory. Therefore, only a portion can be loaded, which means that, in many instances, the relevant entries in the table are still in non-volatile memory. This excessive read to search the table in non-volatile memory is sometimes called a control read and can degrade random read performance, which is an important metric for storage devices in general and embedded devices specifically. Additional volatile memory can be added to a storage system to address this problem, but this can increase the expense and size of the storage system's controller. Some storage systems use compressed table caching mechanisms and algorithms that allows almost zero control reads in several use cases, such as sequential precondition.